Scaling the planar NAND flash cells to the 20nm node and beyond mandates introduction of inter-gate insulators with high dielectric constant (). However, because these insulators provide a smaller electron barrier at the interface with the poly-Si floating gate, the program window and the retention properties of these scaled cells are jeopardized. To reduce the charge loss from the floating to the control gate, one may consider the introduction of a hybrid floating gate (HFG) structure comprised of poly-Si and a high work function (WF) metal, e.g., TiNx (x approximate to 1; WF approximate to 4.7eV) or Ru (WF approximate to 5.3eV). However, the very HFG concept is based on the assumption that electron trapping occurs inside the HFG stack rather than on traps present in the high- insulator. To examine this critical hypothesis, we analyzed the energy distribution of electrons trapped in flash cells with poly-Si(2nm)/TiN (6nm)/Hf0.8Al0.2Ox(19nm, approximate to 15-19)/TiNx (10nm) and Si(2nm)/Ru (1nm)/Hf0.8Al0.2Ox(5nm)/Al2O3 (5nm)/Hf0.8Al0.2Ox (5nm)/TiNx (10nm) trapping gate stacks using the exhaustive photo-depopulation spectroscopy. We found that trapped electron energy levels show a broad distribution (+/- 0.3eV) centred at approximate to 3.2eV below the oxide conduction band. The energy onset of electron de-trapping at approximate to 2.8eV matches the TiNx/HfO2 barrier height found from internal photoemission experiments, indicating that electrons are predominantly trapped inside the HFG.