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| Indexado |
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| DOI | 10.1109/TII.2016.2535255 | ||||
| Año | 2016 | ||||
| Tipo | artículo de investigación |
Citas Totales
Autores Afiliación Chile
Instituciones Chile
% Participación
Internacional
Autores
Afiliación Extranjera
Instituciones
Extranjeras
Real-time Ethernet (RTE) is widely recognized for its potential to provide a unified communication backbone for next-generation heterogeneous distributed systems. However, most of the existing research in RTE technologies has traditionally focused on formal models and theoretical analyzes of timing properties, usually omitting the associated implementation challenges for testing them in practice. This gap between theory and practice prevents experimental validation of the claimed properties, which in turn hinders the pace of innovation and adoption of the technology in industrial settings. This paper aims at narrowing the theory-practice gap by characterizing a comprehensive open-source RTE framework that explores emerging challenges in real-time networking, including the provision of ultra-low latency and jitter, dynamic bandwidth management, and segmentation within large networks. This work integrates research on formal abstractions for dynamic time-division multiple access arbitration and technological insights from modern hardware infrastructure, and uses a representative distributed video processing application to provide reproducible evidence of the achieved properties in multihop Ethernet settings. By leveraging readily available technology and an open-source design, the proposed framework facilitates further exploration and experimental validation of properties that are beyond the scope of current commercial technologies, encouraging evidence-based discussions to accelerate development and adoption of new standards for next-generation industrial networks.
| WOS |
|---|
| Computer Science, Interdisciplinary Applications |
| Engineering, Industrial |
| Automation & Control Systems |
| Scopus |
|---|
| Information Systems |
| Computer Science Applications |
| Electrical And Electronic Engineering |
| Control And Systems Engineering |
| SciELO |
|---|
| Sin Disciplinas |
| Ord. | Autor | Género | Institución - País |
|---|---|---|---|
| 1 | CARVAJAL-KARL, GONZALO JAVIER | Hombre |
Universidad Técnica Federico Santa María - Chile
Univ Waterloo - Canadá University of Waterloo - Canadá |
| 2 | Araneda, Luis | Hombre |
Universidad de Concepción - Chile
|
| 3 | Wolf, Alejandro | Hombre |
Universidad de Concepción - Chile
|
| 4 | FIGUEROA-YEVENES, MAXIMILIANO | Hombre |
Universidad de Concepción - Chile
|
| 5 | Fischmeister, Sebastian | Hombre |
Univ Waterloo - Canadá
University of Waterloo - Canadá |
| Fuente |
|---|
| Fondo Nacional de Desarrollo Científico y Tecnológico (FONDECYT) |
| Fondo Nacional de Desarrollo Científico y Tecnológico |
| Comisión Nacional de Investigación Científica y Tecnológica |
| Natural Sciences and Engineering Research Council of Canada |
| Comisión Nacional de Investigación CientÃfica y Tecnológica |
| Fondo Nacional de Desarrollo CientÃfico y Tecnológico |
| NSERC DG |
| CMC Microsystems |
| Comision Nacional de Investigacion Cientifica y Tecnologica (CONICYT's) scholarships program for post-graduate studies |
| Canada-Chile Leadership Exchange Program |
| Agradecimiento |
|---|
| This work was supported in part by Fondo Nacional de Desarrollo Cientifico y Tecnologico (FONDECYT) under Grant 1151278; in part by Comision Nacional de Investigacion Cientifica y Tecnologica (CONICYT's) scholarships program for post-graduate studies; in part by the Canada-Chile Leadership Exchange Program; in part bt the NSERC DG under Grant 3571212008, Grant ORF-RE03-045, Grant ORF-RE04-036, Grant ORF-RE04-039, Grant APCPJ 386797-09, and Grant CFI 20314; and in part by CMC Microsystems. Paper no. TII-15-1825. |
| This work was supported in part by Fondo Nacional de Desarrollo Científico y Tecnológico (FONDECYT) under Grant 1151278; in part by Comisión Nacional de Investigación Científica y Tecnológica (CONICYT's) scholarships program for post-graduate studies; in part by the Canada-Chile Leadership Exchange Program; in part bt the NSERC DG under Grant 357121- 2008, Grant ORF-RE03-045, Grant ORF-RE04-036, Grant ORF-RE04-039, Grant APCPJ 386797-09, and Grant CFI 20314; and in part by CMC Microsystems. |