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| Indexado |
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| DOI | 10.1109/APEC48143.2025.10977076 | ||
| Año | 2025 | ||
| Tipo |
Citas Totales
Autores Afiliación Chile
Instituciones Chile
% Participación
Internacional
Autores
Afiliación Extranjera
Instituciones
Extranjeras
Submodule (SM) voltage balancing of a modular multilevel converter (MMC) is crucial for stable operation of the converter. The conventional sorting algorithm is usually used to achieve this balance through instantaneous measuring of SM voltages and arm currents. However, in practice, this process utilizes digital out pins from the controller to operate the half-bridge SM switches, which are slower and inaccurate, compared to the embedded PWM interface modules provided in most commercial controllers. This work proposes a voltage balancing technique using a modified sorting algorithm to be compatible with the PWM interface module's output ports for any type of controllers. It performs the required balancing of the capacitors by identifying the required reference voltage signal. The technique is validated experimentally through a three-phase grid connected solar MMC system and the obtained results are presented to show the performance of the proposed technique to balance the SM voltages.
| Revista | ISSN |
|---|---|
| Thirty Fourth Annual Ieee Applied Power Electronics Conference And Exposition (Apec 2019) | 1048-2334 |
| Ord. | Autor | Género | Institución - País |
|---|---|---|---|
| 1 | Elsanabary, Ahmed | - |
Faculty of Engineering- Port Said University - Egipto
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| 2 | Mekhilef, Saad | - |
Swinburne University of Technology - Australia
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| 3 | Aly, Mokhtar | - |
Universidad San Sebastián - Chile
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| 4 | Rodriguez, Jose | - |
Universidad San Sebastián - Chile
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| Fuente |
|---|
| Fondo Nacional de Desarrollo Científico y Tecnológico |
| Agencia Nacional de Investigación y Desarrollo |