Muestra métricas de impacto externas asociadas a la publicación. Para mayor detalle:
| Indexado |
|
||
| DOI | 10.1109/CAE64243.2025.10961954 | ||
| Año | 2025 | ||
| Tipo |
Citas Totales
Autores Afiliación Chile
Instituciones Chile
% Participación
Internacional
Autores
Afiliación Extranjera
Instituciones
Extranjeras
This work presents a Specification-to-Graphic Design System (GDS) generator for an integrated DC-DC converter. The proposed automated generation flow implements the automated analog design of a Three-Level Flying Capacitor (3LFC) DC-DC converter power stage with integrated gate drivers. The presented design flow uses open source tools, such as Magic VLSI and NGSpice, and it was tested on Google Colaboratory platform for reproducibility. Simulation results demonstrate that the proposed automated generator is able to design a fully-operational open-loop 3LFC DC-DC Converter, therefore validating the proposed generator.
| Ord. | Autor | Género | Institución - País |
|---|---|---|---|
| 1 | Osorio R, Vicente | - |
Universidad Técnica Federico Santa María - Chile
|
| 2 | Marin, Jorge | - |
Universidad Técnica Federico Santa María - Chile
|
| 3 | Rojas, Christian A. | - |
Universidad Técnica Federico Santa María - Chile
|
| 4 | Cortes, Alfonso | - |
INRIA Institut National de Recherche en Informatique et en Automatique - Francia
|
| Fuente |
|---|
| Fondo Nacional de Desarrollo Científico y Tecnológico |
| AC3E |
| Agencia Nacional de Investigación y Desarrollo |
| Agradecimiento |
|---|
| This work was supported, in part, by the following projects from the Agencia Nacional de Investigacion y Desarrollo (ANID): AC3E (ANID/BASAL/AFB240002), FONDECYT Initiation Research Project 11240947 and FONDECYT Regular Project 1240537. The authors acknowledge the SSCS IEEE PICO program s Code-a-Chip Travel Grant Award for supporting the presentation of this work at the 2023 VLSI Symposium. |