The resistive RAM (ReRAM) technology is continuously attracting attention from the relevant industry who wish to exploit the potential of such technological advances in emerging applications. To incorporate such memory blocks in any application, a dedicated ReRAM memory control unit (ReMCU) is required, to carry out the READ and WRITE operations correctly and efficiently. Such ReMCU design depends on the target ReRAM organization and its peripheral circuitry. As a first approach to the hardware (HW) development of a ReMCU IP block, we developed a dedicated ReMCU module in digital HW to control the READ and WRITE operations from/to different ReRAM locations. The proposed design assumes a target ReRAM topology which allows independent access to the 1T1R cells in any bitline, thus facilitating parallel READ and WRITE operations with the simultaneous application of SET and RESET voltages. Our first prototype was implemented and tested in a field programmable gate array (FPGA) platform. Using the Vivado Design Suite, we demonstrate experimentally the correct processing and the parallel execution of the READ and WRITE instructions, received from a host PC via a serial communication protocol.