ReRAM cells store digital information in form of resistance using low and high resistance states, whose precise distributions are attributed to the inherent switching variability of the devices. Once the SET & RESET threshold values are known, the WRITE pulse amplitudes are selected only slightly larger, avoiding high amplitudes that could impact the device endurance. However, after several cycles such small pulses frequently cause incomplete transitions in WRITE attempts. We exemplify this with experimental measurements on commercial Self-Directed Channel (SDC) memristive devices. To overcome state transition errors, more comprehensive WRITE schemes are required. In this direction, here we discuss the development of an advanced ReRAM WRITE algorithm, as a first approach towards the design of memory control units for ReRAM modules. The proposed driving scheme contemplates gradual and verified WRITE operations, and can successfully cope with the effects of variability. Its effectiveness was validated via high-level simulations in Python, using a behavioral model of memristive devices, which was significantly enriched to support nonideal performance features. The results demonstrate that advanced ReRAM WRITE schemes could mitigate the effects of variability and improve the performance of memory cells.