Memristive devices emerge as an enabling technology for high-density nonvolatile information storage and for computing accelerators, based on neuromorphic and in-memory logic implementations. Whether such devices store binary or multi-level information, the reliability of READ and WRITE memory operations is an important issue. The control module of the driving circuits of the resistive memory core should handle any problems originating from the nonidealities of memristive cells, and carry out successfully every supported operation. Such nonidealities include variability, fading memory, bias-dependent switching rate, READ-induced drift, and stuck-at ON/OFF faults, to name a few. In this direction, feedback-enriched WRITE schemes constitute a promising approach and here we present the maj or aspects of the design of a comprehensive memory controller, oriented to resistive memories (ReRAM). We describe algorithmically an adequate strategy to follow for precise WRITE operations and validate the correct operation in high-level simulations using Python and a behavioral model of voltage-controlled memristive devices.