The implementation of CA-based models directly in digital hardware (HW) enables their fully-parallel execution and benefits systems supporting time-critical applications. Integrating large CA sizes in HW is desirable for industrial applications, such as in agri-food electronics, but the required HW resources depend on the total number of integrated CA cells and on the desired functionality. Trading parallelism of computation for HW resources is a meaningful strategy to explore, provided that any timing specifications of the target application are still met. In this direction, this paper presents the results of a design exploration aiming to decrease the total amount of resources required for the CA lattice on an FPGA by serializing certain parts of the computations and by introducing heterogeneity to the lattice in HW. We consider the Digilent Nexys DDR board for our experimental work. We compare the synthesis reports of our designs with those of a fully-parallel CA implementation. Our results reveal important gains that the synthesis algorithms can achieve, depending on the functionality of the CA cells and the complexity of the required computations.