The technology of resistive memories (ReRAM), which use memristive storage cells, is being increasingly considered as a promising means for the implementation of neuromorphic computing systems for AI applications. However, major nonidealities of memristive devices such as the variability in the switching performance, pose concerns about the reliability of WRITE procedures in ReRAM. In any computing system employing ReRAM, it is the memory control unit (MCU) which should carry out all the READ/WRITE operations, anticipate hard errors (stuck-at faults), and be able to identify erroneous performance in the memory cells. In this direction, we present the early design steps towards a MCU hardware IP, oriented to the ReRAM relevant industry, which complies with the abovementioned requirements. The digital HW of the MCU was designed in Verilog HDL for a given ReRAM topology and its peripheral circuitry, and is compatible with different memory organizations. Following an algorithmic approach, the MCU carries out READ and supervised WRITE operations. We validated the correctness of the system via functional simulations for key scenarios of interest in Vivado Design Suite.