The use of computational memories based on ReRAM technology is currently being explored for the next-generation energy-efficient computing-in-memory (CIM) systems. Such approach presents major challenges at device, circuit, and application level. Thus, this MSc Thesis work aims to establish a roadmap towards technologically-viable solutions for the design and development of industrially appealing ReRAM-based CIM systems. To this end, we comment on the major steps in the SW-HW co-design to develop the memory array driving circuitry that will support memory and logic operations based on non-stateful logic primitives. The latter are expected to be variability-agnostic and not to rely computations on probabilistic switching of memristors. Furthermore, we highlight the requirement for synthesis algorithms designed adhoc for CIM systems, compatible with the peripheral circuitry of the ReRAM and the underlying logic primitives, which will produce delay/area-efficient execution of an arbitrary logic function in memory. The complete toolkit resulting from the proposed roadmap is expected to accelerate the industrial establishment of resistive CIM systems through the development of functional prototypes, fully compatible with imperfections of ReRAM devices, thus useful for immediate practical exploitation by the relevant industry.