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| DOI | 10.1007/S11276-022-02912-2 | ||||
| Año | 2022 | ||||
| Tipo | artículo de investigación |
Citas Totales
Autores Afiliación Chile
Instituciones Chile
% Participación
Internacional
Autores
Afiliación Extranjera
Instituciones
Extranjeras
This paper presents the design of an interleaver for short Parallel Turbo Codes (PTC) with short block lengths in the order of 64, 128, and 256 bits. In particular, the objective is to design an interleaver that generates decorrelation in the external input information to parallel recursive convolutional encoders, with sufficient data propagation to reduce the Bit Error Rate (BER). Experimental tests are designed and implemented -by numerical calculations- using the MatLab/Simulink software. The S-random interleaver, which applies circular displacement and a propagation constraint, is employed. An excellent reduction in BER is achieved for the three short block lengths, according to the quality indicator defined by the International Telecommunication Union (ITU).
| Ord. | Autor | Género | Institución - País |
|---|---|---|---|
| 1 | URREA-ONATE, CLAUDIO | Hombre |
Universidad de Santiago de Chile - Chile
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| 2 | KERN-MOLINA, JOHN | Hombre |
Universidad de Santiago de Chile - Chile
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| 3 | Lopez-Escobar, Ricardo | Hombre |
Universidad de Santiago de Chile - Chile
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| Fuente |
|---|
| University of Santiago |
| Vicerrectoria de Investigacion, Desarrollo e Innovacion of the University of Santiago of Chile, Chile |
| Vicerrectoría de Investigación, Desarrollo e Innovación of the University of Santiago |