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| DOI | 10.1109/TIE.2018.2844842 | ||||
| Año | 2019 | ||||
| Tipo | artículo de investigación |
Citas Totales
Autores Afiliación Chile
Instituciones Chile
% Participación
Internacional
Autores
Afiliación Extranjera
Instituciones
Extranjeras
This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms.
| Ord. | Autor | Género | Institución - País |
|---|---|---|---|
| 1 | MORA-CASTRO, ANDRES FELIPE | Hombre |
Universidad Técnica Federico Santa María - Chile
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| 2 | Urrutia, Matias | Hombre |
Universidad Técnica Federico Santa María - Chile
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| 3 | RAMIREZ-ALEGRIA, ROBERTO ORLANDO | Hombre |
Universidad de Chile - Chile
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| 4 | ANGULO-CARDENAS, ALEJANDRO ALBERTO | Hombre |
Universidad Técnica Federico Santa María - Chile
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| 5 | Espinoza, Mauricio | Hombre |
UNIV COSTA RICA - Costa Rica
Universidad de Costa Rica - Costa Rica |
| 6 | DIAZ-DIAZ, MATIAS DAVID | Hombre |
Universidad de Santiago de Chile - Chile
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| 7 | LEZANA-ILLESCA, PABLO | Hombre |
Universidad Técnica Federico Santa María - Chile
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| Fuente |
|---|
| CONICYT |
| FONDECYT Chile |
| Basal Project "Advanced Center for Electrical and Electronic Engineering |
| Conicyt Grant CONICYT-PCHA/Doctorado |
| Agradecimiento |
|---|
| This work was supported in part by Fondecyt Chile under Grant 1180879 and Grant 11170229; and in part by the Basal Project FB0008 "Advanced Center for Electrical and Electronic Engineering." The work of A. Mora was supported by the Conicyt Grant CONICYT-PCHA/Doctorado Nacional/2013-21130042. |
| Manuscript received September 15, 2017; revised February 15, 2018 and May 11, 2018; accepted May 21, 2018. Date of publication June 13, 2018; date of current version October 31, 2018. This work was supported in part by Fondecyt Chile under Grant 1180879 and Grant 11170229; and in part by the Basal Project FB0008 “Advanced Center for Electrical and Electronic Engineering.” The work of A. Mora was supported by the Conicyt Grant CONICYT-PCHA/Doctorado Nacional/2013-21130042. (Corresponding author: Andrés Mora.) A. Mora, M. Urrutia, A. Angulo, and P. Lezana are with the Department of Electrical Engineering, Universidad Técnica Federico Santa María, Valparaíso 8370071, Chile (e-mail: a.mora@ieee.org; maturrutia@ gmail.com; alejandro.angulo@usm.cl; pablo.lezana@usm.cl). |