Despite recent technological advances which improve their performance and reduce their cost, Focal Plane Arrays for infrared imagers suffer from spatial nonuniformity that renders their output unusable unless a suitable correction method is applied. This paper describes an embedded hardware implementation of Scribner's algorithm for online nonuniformity correction. Our implementation on a Xilinx Spartan XC3S1200E FPGA achieves a throughput of more than 130 frames per second on 320x240-pixel IR video, which greatly exceeds real-time requirements. The power consumption of our system is 329mW, which is two orders of magnitude smaller than a software implementation of the algorithm on a traditional processor, and can be greatly reduced with a custom-VLSI implementation of the architecture. © 2012 IEEE.